This invention relates to data processing systems and in particular, to data processing systems that are configured with field effect transistors on a single chip, and more particularly, to input buffer circuits associated with data processing systems that are implemented with field effect transistors on a single integrated circuit chip.
Data processing systems that are implemented on a single chip with field effect transistors are inherently slow, although economical to produce, due to the necessity of using multiple clocks to execute the associated or desired functions. Traditionally, a first clock is used to precharge the data lines, a second clock is used to set up the precharged data lines in circuits for receipt of data, and a third clock is used to implement the desired function. In applications where speed is not a necessary constraint on the application of the product, such as a hand-held calculator, the generation of clock signals with multiple phases allows the implementation of these circuits with relative ease. However, when the application of the devices is in an environment where speed is of the essence, and there are only a few clock phases provided, then the traditional method of implementing the field effect transistor circuits is difficult due to the limited number of clock phases and the additional requirement that the functions must be implemented within a single clock cycle.
Field effect transistor logic circuits operate with logic levels of nominally 0 V and 5 V, whereas the interface of the chip is based on TTL (Transistor/Transistor Logic) voltage levels where 0.8 V must be recognized as a low level and 2.0 V must be recognized as a high level. As cycle times have decreased a fast means to convert from TTL to field effect transistor logic circuits voltage levels have become necessary.